1. Field of the invention
The present invention relates, in general, to a method for constructing a highly integrated semiconductor connecting device, and more particularly to improvements in scaling the device down and in device reliability as a result of the method.
2. Description of the Prior Art
Generally, in fabricating a semiconductor device, a plurality of first conductive lines, a first interlayer insulating film, a plurality of second conductive lines and a second insulating film are formed, in due order, and then, a plurality of third conductive lines are formed over the second interlayer insulating film, the respective third conductive line passing between the second conductive lines and being connected with the first conductive line through respective third conductive line contact formed on the first conductive line. At this time, the third conductive line contact has to be spaced out from the second conductive line by a predetermined distance in order to insulate the third conductive line from the second conductive line.
Accordingly, in designing a connecting part in a highly integrated semiconductor device, the third conductive line contact mask and the second conductive line mask have to comply with a design rule.
That is, the second conductive line mask and the third conductive line contact mask to connect the third conductive line with the first conductive line have to be designed in such a way that the third conductive line contact is spaced out from the second conductive line by a predetermined distance. This restriction causes registration and critical dimension variation between the third conductive line and the second conductive line mask when the mask is made. In addition to this misalignment problem focus error of lens and critical dimension variation are generated when forming a pattern on a wafer. What is worse than any other problem is the increment of the connecting part in size because of the thickness of the insulating film formed between the third conductive line contact and the second conductive line.
For convenience, description for a method for connecting a charge storage electrode (the third conductive line) with a source electrode (the first conductive line) concurrently with insulating the charge storage electrode (the third conductive line) from a bit line (the first conductive line) in a DRAM cell structure, is to be given next.
Referring now to FIG. 1, there is a plan view showing generally only important mask layers necessary to form a self-aligned contact of connecting device in a DRAM cell structure, wherein reference letter A designates a plurality of spaced-apart source electrode masks while reference letters B, and C.sub.1 and C.sub.2 show respectively a plurality of spaced-apart bit line masks, and two types of charge storage electrode masks which can be alternatively employed in the present invention. As shown in FIG. 1, the charge storage electrode contact mask C.sub.2 is to maximize the size of the charge storage electrode contact formed.
Prior art relating to the construction of highly integrated semiconductor connecting devices will be, in essence, explained with reference to several figures, wherein reference numeral 1 designates a semiconductor substrate, whereas other reference numerals 2, 3, 4, 5, 7, 8, 13', 18, 18' and 23 show a plurality of device separation insulating films, a plurality of source electrodes, a first interlayer insulating film, a plurality of bit lines, a photosensitive film (the charge storage electrode contact mask), a second interlayer insulating film, a plurality of charge storage electrodes, an insulating film for forming a spacer, an insulating film spacer and a remnant of conductive material for the charge storage electrode, respectively.
Referring initially to FIG. 3A, there is, in part, illustrated a construction method for a connecting device, taken generally through section line A--A' of FIG. 1. As illustrated in this figure, the conventional connecting device is constructed by sectioning firstly the semiconductor substrate 1 into active regions and device separation regions by means of the formation of the device separation insulating films 2 in the device separation regions.
The source electrodes 3 are formed in the active regions, followed by the formation of the first interlayer insulating film 4, a conductive material for the bit line and the second interlayer insulating film 8 over the resulting substrate, in due order.
Using the bit line mask of FIG. 1, an etch process is applied to the first interlayer insulating film 4, the conductive material for the bit lines and the second interlayer insulating film 8 to remove them atop the source electrodes 3. As a result, the bit lines 5 intercalated between the first interlayer film 4 and the second interlayer film 8 are formed, overlaying the device separation insulating films 2.
Following this, the insulating film 18 for creating a spacer is formed over the resulting structure including the exposed source electrodes 3 and the bit lines 5 intercalated between the first and, the second insulating films.
On the insulating film 18, a photosensitive film is coated, so as to form a charge storage electrode contact mask 7 (see FIG. 3A).
When the etch process is applied, the first interlayer insulating film 4 is etched in such a way that either the surface of the source electrode 3 is exposed thoroughly, or the first interlayer insulating film 4 is left thin.
Other insulating spacers may be formed at the side walls of the bit lines 5 in advance of the formation of the insulating film 18 which is to insulate the bit line 5 (the second conducive line as explained above) from the charge storage electrode (the third conductive line as explained above) to be formed later.
FIG. 3A shows that the charge storage electrode contact mask 7 can be is positioned in such a way as to cover a major part of the bit line 5 and to expose a minor part thereof. That is, the vertical axis passing the center of the charge storage electrode contact mask 7 can be spaced from the vertical axis passing the center of the bit line 5 by a the maximal distance depending on how the mask is made.
Referring now to FIG. 3B, there is illustrated the conventional construction method for a connecting device, continued from the FIG. 3A. As shown in this drawing, the charge storage electrodes 13' (the third conductive lines) are connected with the source electrodes 3 (the first conductive lines), being insulated from-the bit lines 5 (the second conductive lines).
For this, the insulating film 18 for creating a spacer is initially subjected to the treatment of etching by use of the charge storage electrode contact mask 7 to remove a predetermined thickness of the insulating film 18. As a result, the source electrodes 3 are exposed and the insulating films 3 and 18' for insulation are left over the bit lines; 5 and at the side walls thereof.
A conductive material for charge storage electrode is entirely deposited and then, subjected to the treatment of etching by use of the charge storage electrode mask so as to form the charge storage electrodes 13'.
With the above conventional method, the third conductive line is satisfactorily connected with the first conductive line, being securely insulated from the second conductive line.
However, when the connecting device is constructed by the conventional method described above, there is formed a steep stepped part which causes problems in a fabricated semiconductor device. For example, after applying the etch process to the conductive material for charge storage electrode deposited entirely in order to form the charge storage, a remnant material 23, as shown in FIG. 3B, remains at a steep stepped part formed by the first interlayer insulating film 4, the bit line 5 and the second interlayer insulating film 8. A short circuit may be formed between the remnant material and the neighboring charge storage electrode, degrading the fabricated semiconductor device.
Another conventional example is to be described again with reference to FIGS. 2A and 2B, taken generally through section line A--A' of FIG. 1.
Firstly, the semiconductor substrate 1 is sectioned into active regions and device separation regions by the formation of the device separation insulating films 2 in the device separation regions, as shown in FIG. 2A.
The source electrodes 3 are formed in the active regions, followed by the formation of the first interlayer insulating film 4 over the resulting structure including the source electrodes 3 and the device separation insulating films 2.
Over the first interlayer insulating film 4 are formed the bit lines 5 in a predetermined pattern which are subsequently covered with the second interlayer insulating film 8 for planarization.
Using the charge storage electrode contact mask, an etch process is applied to the second interlayer insulating film 8 and the first interlayer insulating film 4 to remove them atop the source electrode 3 and thus, to expose the source electrode 3.
Thereafter, the insulating film 18 for creating a spacer is entirely deposited over the resulting structure to insulate the bit lines 5.
FIG. 2A shows that the second insulating film 8 is formed in such a way to expose the partial upper surface and the one side wall of the bit line 5 and to cover others portions thereof. This is based on the fact that the vertical axis passing the center of the charge storage electrode contact mask positioned on the second insulating film can be spaced from the vertical axis passing the center of the bit line 5 by a maximal distance depending on how the mask is made.
The exposure of the bit lines 5 causes a problem with regard to the thickness of the spacer insulating film 18. For example, if the spacer insulating film is too thick, the area of contact can be so small that the charge storage electrode is difficult to connect with the source electrode. On the other hand, if the spacer insulating film is too thin, the side wall of the, spacer insulating film is aligned with the side wall of the exposed bit line 5, such that the bit lines 5 cannot be insulated sufficiently.
Turning now to FIG. 2B, there is illustrated an etch back which is applied to the insulating film 18 so as to form insulating spacers 18' at the exposed side walls of the bit lines 5.
The another conventional method can reduce the steepness of the stepped part, as shown in FIG. 2B.
However, as mentioned above, the another conventional method has difficulty in controlling the thickness of the insulating film for creating a spacer. That is, thick insulating film prevents the connection of the third conductive line with the first conductive line whereas thin insulating film results in incomplete insulation of the third conductive line from the second conductive line.
What is worse, since the second interlayer insulating film 8 covers partially the bit lines 5, the spacer formed from the insulating film 18 cannot insulate the upper surface of the bit line sufficiently in spite of sufficient insulating the side wall of the bit line.
Accordingly, the another conventional method is apt to generate a short circuit between the charge storage electrode and the bit line, degrading the semiconductor device manufactured thereby.
In addition, a little reduction of the distance between the charge storage electrode contact mask and the bit line affects the contact area, resulting in the disconnection of the charge storage electrode with the source electrode.
As a result, the connecting device cannot be sufficiently scaled down by the conventional method because the area of connecting part is restricted.